// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_ap_iob_rx_am_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:14 Create file
// ******************************************************************************

#ifndef __HIPCIEC_AP_IOB_RX_AM_REG_REG_OFFSET_FIELD_H__
#define __HIPCIEC_AP_IOB_RX_AM_REG_REG_OFFSET_FIELD_H__

#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_AXUSER_UPDATE_EN_0_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_AXUSER_UPDATE_EN_0_OFFSET     8
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_WR_EN_0_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_WR_EN_0_OFFSET       5
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_RD_EN_0_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_RD_EN_0_OFFSET       4
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_PARTIAL_WRITE_64BYTE_0_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_PARTIAL_WRITE_64BYTE_0_OFFSET 3
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_WR_256BYTE_0_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_WR_256BYTE_0_OFFSET        2
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_RD_256BYTE_0_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_RD_256BYTE_0_OFFSET        1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_SHUTDOWN_REQ_0_LEN            1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_SHUTDOWN_REQ_0_OFFSET         0

#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_AXUSER_UPDATE_EN_1_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_AXUSER_UPDATE_EN_1_OFFSET     8
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_WR_EN_1_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_WR_EN_1_OFFSET       5
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_RD_EN_1_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_RD_EN_1_OFFSET       4
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_PARTIAL_WRITE_64BYTE_1_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_PARTIAL_WRITE_64BYTE_1_OFFSET 3
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_WR_256BYTE_1_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_WR_256BYTE_1_OFFSET        2
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_RD_256BYTE_1_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_RD_256BYTE_1_OFFSET        1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_SHUTDOWN_REQ_1_LEN            1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_SHUTDOWN_REQ_1_OFFSET         0

#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_AXUSER_UPDATE_EN_2_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_AXUSER_UPDATE_EN_2_OFFSET     8
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_WR_EN_2_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_WR_EN_2_OFFSET       5
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_RD_EN_2_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_LAT_STAT_RD_EN_2_OFFSET       4
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_PARTIAL_WRITE_64BYTE_2_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_PARTIAL_WRITE_64BYTE_2_OFFSET 3
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_WR_256BYTE_2_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_WR_256BYTE_2_OFFSET        2
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_RD_256BYTE_2_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_EN_RD_256BYTE_2_OFFSET        1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_SHUTDOWN_REQ_2_LEN            1
#define HIPCIEC_AP_IOB_RX_AM_REG_CTRL_SHUTDOWN_REQ_2_OFFSET         0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_WR_TRANS_CTRL_0_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_WR_TRANS_CTRL_0_OFFSET 8
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_RD_TRANS_CTRL_0_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_RD_TRANS_CTRL_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_WR_TRANS_CTRL_1_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_WR_TRANS_CTRL_1_OFFSET 8
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_RD_TRANS_CTRL_1_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_RD_TRANS_CTRL_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_WR_TRANS_CTRL_2_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_WR_TRANS_CTRL_2_OFFSET 8
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_RD_TRANS_CTRL_2_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_RD_TRANS_CTRL_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWQOS_CTRL_0_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_AWQOS_CTRL_0_OFFSET 4
#define HIPCIEC_AP_IOB_RX_AM_REG_ARQOS_CTRL_0_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_ARQOS_CTRL_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWQOS_CTRL_1_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_AWQOS_CTRL_1_OFFSET 4
#define HIPCIEC_AP_IOB_RX_AM_REG_ARQOS_CTRL_1_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_ARQOS_CTRL_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWQOS_CTRL_2_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_AWQOS_CTRL_2_OFFSET 4
#define HIPCIEC_AP_IOB_RX_AM_REG_ARQOS_CTRL_2_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_ARQOS_CTRL_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STASH_MODE_0_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STASH_MODE_0_OFFSET        11
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_TYPE_MODE_0_LEN            2
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_TYPE_MODE_0_OFFSET         8
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_CLEANINVALID_MODE_0_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_CLEANINVALID_MODE_0_OFFSET 5
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FNA_MODE_0_LEN             1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FNA_MODE_0_OFFSET          4
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FA_MODE_0_LEN              2
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FA_MODE_0_OFFSET           2
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_MODE_0_LEN             1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_MODE_0_OFFSET          1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_MODE_0_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_MODE_0_OFFSET       0

#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STASH_MODE_1_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STASH_MODE_1_OFFSET        11
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_TYPE_MODE_1_LEN            2
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_TYPE_MODE_1_OFFSET         8
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_CLEANINVALID_MODE_1_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_CLEANINVALID_MODE_1_OFFSET 5
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FNA_MODE_1_LEN             1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FNA_MODE_1_OFFSET          4
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FA_MODE_1_LEN              2
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FA_MODE_1_OFFSET           2
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_MODE_1_LEN             1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_MODE_1_OFFSET          1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_MODE_1_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_MODE_1_OFFSET       0

#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STASH_MODE_2_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STASH_MODE_2_OFFSET        11
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_TYPE_MODE_2_LEN            2
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_TYPE_MODE_2_OFFSET         8
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_CLEANINVALID_MODE_2_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_CLEANINVALID_MODE_2_OFFSET 5
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FNA_MODE_2_LEN             1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FNA_MODE_2_OFFSET          4
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FA_MODE_2_LEN              2
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_FA_MODE_2_OFFSET           2
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_MODE_2_LEN             1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_MODE_2_OFFSET          1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_MODE_2_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_MODE_2_OFFSET       0

#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_SET_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_SET_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_SET_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_SET_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_SET_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_STRMID_SET_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_SET_0_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_SET_0_OFFSET 16

#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_SET_1_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_SET_1_OFFSET 16

#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_SET_2_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_ARUSER_SSV_SET_2_OFFSET 16

#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_READCLEAN_THRESHOLD_0_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_READCLEAN_THRESHOLD_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_READCLEAN_THRESHOLD_1_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_READCLEAN_THRESHOLD_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_READCLEAN_THRESHOLD_2_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_READCLEAN_THRESHOLD_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_MODE_0_LEN     1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_MODE_0_OFFSET  11
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_MODE_0_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_MODE_0_OFFSET     10
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_TYPE_MODE_0_LEN      2
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_TYPE_MODE_0_OFFSET   8
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FP_MODE_0_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FP_MODE_0_OFFSET     6
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FNA_MODE_0_LEN       1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FNA_MODE_0_OFFSET    4
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FA_MODE_0_LEN        2
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FA_MODE_0_OFFSET     2
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_MODE_0_LEN       1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_MODE_0_OFFSET    1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_MODE_0_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_MODE_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_MODE_1_LEN     1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_MODE_1_OFFSET  11
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_MODE_1_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_MODE_1_OFFSET     10
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_TYPE_MODE_1_LEN      2
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_TYPE_MODE_1_OFFSET   8
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FP_MODE_1_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FP_MODE_1_OFFSET     6
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FNA_MODE_1_LEN       1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FNA_MODE_1_OFFSET    4
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FA_MODE_1_LEN        2
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FA_MODE_1_OFFSET     2
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_MODE_1_LEN       1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_MODE_1_OFFSET    1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_MODE_1_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_MODE_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_MODE_2_LEN     1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_MODE_2_OFFSET  11
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_MODE_2_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_MODE_2_OFFSET     10
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_TYPE_MODE_2_LEN      2
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_TYPE_MODE_2_OFFSET   8
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FP_MODE_2_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FP_MODE_2_OFFSET     6
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FNA_MODE_2_LEN       1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FNA_MODE_2_OFFSET    4
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FA_MODE_2_LEN        2
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_FA_MODE_2_OFFSET     2
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_MODE_2_LEN       1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_MODE_2_OFFSET    1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_MODE_2_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_MODE_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_SET_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_SET_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_SET_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_SET_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_SET_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STRMID_SET_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_SET_0_LEN      1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_SET_0_OFFSET   16
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_SET_0_LEN       4
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_SET_0_OFFSET    12
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_SET_0_LEN    11
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_SET_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_SET_1_LEN      1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_SET_1_OFFSET   16
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_SET_1_LEN       4
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_SET_1_OFFSET    12
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_SET_1_LEN    11
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_SET_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_SET_2_LEN      1
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SSV_SET_2_OFFSET   16
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_SET_2_LEN       4
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_SO_SET_2_OFFSET    12
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_SET_2_LEN    11
#define HIPCIEC_AP_IOB_RX_AM_REG_AWUSER_STASH_SET_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_VIOLATE_THRESHOLD_0_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_VIOLATE_THRESHOLD_0_OFFSET 4
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_WR_OPTIMIZE_0_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_WR_OPTIMIZE_0_OFFSET       0

#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_VIOLATE_THRESHOLD_1_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_VIOLATE_THRESHOLD_1_OFFSET 4
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_WR_OPTIMIZE_1_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_WR_OPTIMIZE_1_OFFSET       0

#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_VIOLATE_THRESHOLD_2_LEN    4
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_VIOLATE_THRESHOLD_2_OFFSET 4
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_WR_OPTIMIZE_2_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_CFG_SO_WR_OPTIMIZE_2_OFFSET       0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_WR_TRANS_0_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_WR_TRANS_0_OFFSET 8
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_RD_TRANS_0_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_RD_TRANS_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_WR_TRANS_1_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_WR_TRANS_1_OFFSET 8
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_RD_TRANS_1_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_RD_TRANS_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_WR_TRANS_2_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_WR_TRANS_2_OFFSET 8
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_RD_TRANS_2_LEN    8
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_MAX_RD_TRANS_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_AT_DATA_VALID_STS_0_LEN     1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_AT_DATA_VALID_STS_0_OFFSET  4
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_ODR_DATA_VALID_STS_0_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_ODR_DATA_VALID_STS_0_OFFSET 3
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_WVALID_STS_0_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_WVALID_STS_0_OFFSET     2
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_ODR_SBM_REQ_STS_0_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_ODR_SBM_REQ_STS_0_OFFSET       1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_REQ_STS_0_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_REQ_STS_0_OFFSET        0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_AT_DATA_VALID_STS_1_LEN     1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_AT_DATA_VALID_STS_1_OFFSET  4
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_ODR_DATA_VALID_STS_1_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_ODR_DATA_VALID_STS_1_OFFSET 3
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_WVALID_STS_1_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_WVALID_STS_1_OFFSET     2
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_ODR_SBM_REQ_STS_1_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_ODR_SBM_REQ_STS_1_OFFSET       1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_REQ_STS_1_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_REQ_STS_1_OFFSET        0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_AT_DATA_VALID_STS_2_LEN     1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_AT_DATA_VALID_STS_2_OFFSET  4
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_ODR_DATA_VALID_STS_2_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_ODR_DATA_VALID_STS_2_OFFSET 3
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_WVALID_STS_2_LEN        1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_WVALID_STS_2_OFFSET     2
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_ODR_SBM_REQ_STS_2_LEN          1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_ODR_SBM_REQ_STS_2_OFFSET       1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_REQ_STS_2_LEN           1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_DAT_REQ_STS_2_OFFSET        0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WDATA_ERROR_STS_0_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WDATA_ERROR_STS_0_OFFSET 3
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_ERROR_STS_0_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_ERROR_STS_0_OFFSET 2
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RDATA_ERROR_STS_0_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RDATA_ERROR_STS_0_OFFSET 1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_ERROR_STS_0_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_ERROR_STS_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WDATA_ERROR_STS_1_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WDATA_ERROR_STS_1_OFFSET 3
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_ERROR_STS_1_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_ERROR_STS_1_OFFSET 2
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RDATA_ERROR_STS_1_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RDATA_ERROR_STS_1_OFFSET 1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_ERROR_STS_1_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_ERROR_STS_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WDATA_ERROR_STS_2_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WDATA_ERROR_STS_2_OFFSET 3
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_ERROR_STS_2_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_BRESP_ERROR_STS_2_OFFSET 2
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RDATA_ERROR_STS_2_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RDATA_ERROR_STS_2_OFFSET 1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_ERROR_STS_2_LEN    1
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RRESP_ERROR_STS_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_GEN_REQ_0_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_GEN_REQ_0_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_GEN_REQ_0_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_GEN_REQ_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_GEN_REQ_1_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_GEN_REQ_1_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_GEN_REQ_1_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_GEN_REQ_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_GEN_REQ_2_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_GEN_REQ_2_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_GEN_REQ_2_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_GEN_REQ_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_0_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_0_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_0_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_0_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_0_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_0_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_1_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_1_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_1_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_1_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_1_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_1_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_2_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_2_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_2_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_2_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_2_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_2_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_3_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_3_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_3_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_3_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_3_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_RD_TXID_STS_3_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_0_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_0_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_0_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_0_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_0_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_0_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_1_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_1_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_1_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_1_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_1_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_1_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_2_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_2_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_2_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_2_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_2_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_2_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_3_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_3_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_3_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_3_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_3_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_CURR_WR_TXID_STS_3_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_0_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_0_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_0_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_0_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_0_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_0_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_1_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_1_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_1_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_1_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_1_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_1_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_2_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_2_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_2_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_2_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_2_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_2_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_3_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_3_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_3_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_3_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_3_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_RRESP_CONFLICT_3_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_0_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_0_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_0_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_0_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_0_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_0_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_1_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_1_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_1_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_1_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_1_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_1_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_2_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_2_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_2_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_2_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_2_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_2_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_3_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_3_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_3_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_3_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_3_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_BRESP_CONFLICT_3_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_RD_LATENCY_0_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_RD_LATENCY_0_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_RD_LATENCY_0_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_RD_LATENCY_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_RD_LATENCY_1_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_RD_LATENCY_1_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_RD_LATENCY_1_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_RD_LATENCY_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_RD_LATENCY_2_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_RD_LATENCY_2_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_RD_LATENCY_2_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_RD_LATENCY_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_RD_LATENCY_0_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_RD_LATENCY_0_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_RD_LATENCY_0_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_RD_LATENCY_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_RD_LATENCY_1_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_RD_LATENCY_1_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_RD_LATENCY_1_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_RD_LATENCY_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_RD_LATENCY_2_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_RD_LATENCY_2_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_RD_LATENCY_2_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_RD_LATENCY_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_WR_LATENCY_0_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_WR_LATENCY_0_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_WR_LATENCY_0_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_WR_LATENCY_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_WR_LATENCY_1_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_WR_LATENCY_1_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_WR_LATENCY_1_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_WR_LATENCY_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_WR_LATENCY_2_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_MEM_WR_LATENCY_2_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_WR_LATENCY_2_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_MEM_WR_LATENCY_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_WR_LATENCY_0_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_WR_LATENCY_0_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_WR_LATENCY_0_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_WR_LATENCY_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_WR_LATENCY_1_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_WR_LATENCY_1_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_WR_LATENCY_1_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_WR_LATENCY_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_WR_LATENCY_2_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_MAX_P2P_WR_LATENCY_2_OFFSET 16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_WR_LATENCY_2_LEN    16
#define HIPCIEC_AP_IOB_RX_AM_REG_AVA_P2P_WR_LATENCY_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_0_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_0_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_0_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_0_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_0_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_0_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_1_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_1_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_1_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_1_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_1_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_1_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_2_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_2_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_2_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_2_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_2_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_2_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_3_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_3_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_3_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_3_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_3_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_RD_TLP_PAYLOAD_3_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_0_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_0_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_0_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_0_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_0_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_0_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_1_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_1_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_1_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_1_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_1_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_1_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_2_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_2_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_2_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_2_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_2_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_2_2_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_3_0_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_3_0_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_3_1_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_3_1_OFFSET 0

#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_3_2_LEN    32
#define HIPCIEC_AP_IOB_RX_AM_REG_DFX_WR_TLP_PAYLOAD_3_2_OFFSET 0

#endif // __HIPCIEC_AP_IOB_RX_AM_REG_REG_OFFSET_FIELD_H__
